This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-303931, filed on Sep. 28, 2001; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device and also to a semiconductor device.
2. Description of the Related Art
The demand for miniaturization of individual semiconductor devices and large-scale integration of such devices has been and still is increasing to realize high-speed operation and also to attain versatile functionality of semiconductor circuits. However, for successful shrinkage of the device dimensions, various related difficulties are to be overcome. Such difficulties will be understood when considering miniaturization of a MOSFET which comprises an integral part of a semiconductor circuit.
For instance, with reduction of a channel length (i.e., length of the gate electrode) of the MOSFET, its threshold voltage decreases (i.e., short channel effect). If the threshold voltage decreases from an intended value, the MOSFET will operate in an unexpected way and may impair the entire function of the circuit. Moreover, the extent of the voltage drop depends sharply on the physical length of the gate electrode. It entails that, for fabrication of small dimension MOSFET""s, a minor variation of the gate length originated from a process fluctuation of gate electrode formation will result in a large deviation of the threshold voltage. This short channel effect becomes especially problematic when a circuit requires a large number of MOSFET""s with an identical function (such as dynamic random memories, DRAM). The strict requirements for the functional uniformity of the individual device can be satisfied only through an extremely tight quality control of the manufacturing processes, thus restricting the manufacturability of integrated circuits such as DRAMs.
The short channel effect is caused when distortion of electric field in the vicinity of the source and drain electrodes comes to influence the electric field around the center of the channel with the reduction of the channel length. The influence can be avoided by bringing the pn junction formed by the source and the drain closer to the semiconductor surface (i.e., by making the source and drain shallower). However, when the source and drain are simply made shallow, the electric resistance of the source and electrodes increases and obstructs high speed transmission of signals through the device.
To counter this problem, it is a common practice that upper portions of the source and drain regions are chemically combined with a metal to produce a compound (silicidation) which shows significantly lower resistivity than silicon. Metals that can be used for silicidation include Co, Ti and Ni, of which Co is most suitable. This is because it does not show any rise in the electric resistance when it is formed on thin lines (i.e., lack of narrow line effects) and is stable at high temperature. These preferable characteristics of the Co silicidation stand LSI fabrication in good stead.
However, during the silicidation reaction, metal atoms quickly diffuse into the silicon substrate and eventually penetrate the junctions forming the source and drain electrodes if the source and drain are made shallow. When the metal atoms migrate beyond the junctions of the source and drain, they generate leakage currents through the junctions. And source and drain electrodes stop functioning properly.
In fact, the metal atoms diffuse very quickly. In the case of Co, the Co atoms reach a depth of 150 nm even during the silicidation process at 800xc2x0 C. for 30 seconds. FIG. 6 shows leakage levels of n+/p junctions with 35 nm-thick CoSi2 layer thereon as a function of the junction depth (the depth includes the 35 nm of the silicide layer thickness). For reference, leakage levels of silicide-less junctions are also plotted. From FIG. 6, a sizable increase of the leakage current is already evidenced at the depth of 150 nm from the surface, which is by far deeper than the bottom of the silicide film. The increase is due to a rapid migration of the Co atoms into the silicon substrate. In general, rapid diffusion of metal atoms proceeds inevitably along the interfaces between metal and silicon during the silicidation reaction. The metal atoms that have penetrated deep into the silicon substrate form generation-recombination centers in the band gap of silicon and mediate junction leakage currents. If such gap states are formed in the source/drain junctions, leak currents flow through the source/drain electrodes towards the silicon substrate. Then, the function of the MOSFET is impaired. When the MOSFET constitutes a part of a DRAM""s memory cell, the data stored in the cell will be lost and the semiconductor circuit will no longer operate properly.
To alleviate this problem, a technique (known as elevated source/drain method) for selective formation of additional silicon layers on the source and drain regions are developed. With this technique, the surf aces of the semiconductor substrate, where the source and drain electrodes are to be formed, are raised above the original semiconductor surface (where the channel is formed). Then, over the additionally elevated surfaces, pn junction formation for the source and drain regions and the silicidation process are performed. The junctions formed in this way can be located at a shallow position relative to the original surface of the semiconductor substrate, while maintaining a deep position as viewed from the newly elevated surfaces of source and drain regions. Hence, a sufficient thickness of the source/drain electrodes can be secured.
Such a selective elevation of source and drain surfaces can be realized by using a technique known as selective epitaxial growth. However, for this technique to be successfully applied to actual device fabrication, the final position of the resulting pn junction of the source/drain regions needs to be precisely positioned at the original semiconductor surface (where the channel is formed) or be located slightly below it. This is because drivability of the MOSFET is remarkably reduced if the junction is located above the original surface (the channel interface), whereas a severe short channel effect appears if the junctions are located far below the original surface.
However, the epitaxial growth is very sensitive to the state of the substrate surface on which the selective silicon growth is to be achieved. For instance, the thickness of the silicon film grown on the substrate varies depending on the roughness or crystalline structure of the substrate surface. Also, the quality of the grown film (i.e., the presence/absence of the crystalline defects in the film) depends on the surface condition of the substrate. Thus, for example, incomplete removal of a native oxide on the substrate surface or residual process-damage incurred during gate electrode formation may well result in severe variation in the film thickness between individual devices for which elevation of source and drain regions is attempted.
If the thickness of the additionally formed silicon films is not uniform, it is very difficult to place pn junctions of source/drain regions near the original surface of the semiconductor substrate (where the channel is formed) in a controlled manner. Impurities for the source/drain formation are introduced through the surfaces of the additionally formed silicon films. Non-uniform thickness of the additionally formed silicon films makes the relative distances from their surfaces to the original semiconductor surface (i.e., channel surface) indefinite. Thus, the junctions cannot be accurately placed at the original semiconductor surface whose location is indefinite relative to the surfaces from where the impurities are introduced.
Likewise, if the quality of the grown silicon films differs from a device to a device, it becomes difficult to place the pn junctions precisely at the targeted position near the original semiconductor surface. This is because, the presence of crystal defects in the film (i.e., the film quality) greatly influences the speed of impurity diffusion in the film (e.g., transient enhanced diffusion). It entails that a predetermined thermal diffusion of the impurity for the junction formation could result in non-uniform junction depth due to unexpected impurity diffusion caused by the crystal defects in the film.
Similarly, the diffusion of metal atoms during silicidation is also subject to the quality of the grown silicon films. Thus, even when the source and drain regions are raised by the additional silicon films, if their thickness and quality are non-uniform, metal atoms can easily diffuse and penetrate the junctions at points where the film thickness is thin or the film quality is low. It follows that the non-uniformity of the film thickness and quality limits the effectiveness of the epitaxial growth to counter the leakage generation by the silicidation process.
Furthermore, the metal diffusion in a silicon crystal is very fast itself. Accordingly, in order to block the metal diffusion effectively, the additional silicon layer must be very thick (i.e., thicker than 150 nm). However, due to above-describe reasons, it is almost impossible to selectively and uniformly grow silicon layers as thick as 150 nm on the individual source and drain regions.
Moreover, the height of the source and drain regions, raised by 150 nm, almost equals the height of the gate electrodes. The lack of the height-difference makes it difficult to ensure electrical isolation between gate electrodes and source/drain regions when silicidation process is applied to these electrodes and regions simultaneously (SALICIDE (self-align-silicide) process).
In addition, a selectively grown silicon film tends to become thinner in a region adjacent to a gate electrode (which is an intrinsic characteristic of the epitaxial growth). Prior to the silicidation process, the shortest distance between a metal film deposited on the device surface and the source/drain junction is determined at this portion. Hence it is this thinner region that could eventually limit the film""s ability to block the metal diffusion regardless of the thickness of the additional silicon films grown elsewhere.
As described above, in manufacturing of a small-dimension MOSFET device, a silicide layer must be formed on source and drain regions to secure low electrical resistance of the regions while keeping a shallow junction position of the source and drain regions. However, fast metal diffusion during the silicide reaction easily penetrates the shallow junctions and induces leakage. To counter the leakage generation, source and drain regions could be elevated by selective epitaxial growth. Even with this elevation, the fast metal diffusion requires that a silicon layer must be selectively grown to a thickness almost equal to the height of a gate electrode. Unfortunately, however, it is very difficult to form such a thick film having a uniform thickness and quality with this method.
Thus, it is the object of the present invention to provide a semiconductor device that has a SALICIDE structure with low leakage currents and a source/drain height lower than the gate electrode, while maintaining shallow source and drain regions, without the above identified problems of conventional methods. It is also the object of the present invention to provide a method of manufacturing such a semiconductor device.
In an aspect of the invention, the above object is achieved by providing a method of manufacturing a semiconductor device comprising:
forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other, a gate insulating film between the source region and the drain region on the first semiconductor layer and a gate electrode on the gate insulating film;
forming a metal silicide layer showing a first compound phase on the source region, the drain region and the gate electrode;
forming a second semiconductor layer on the metal silicide layer showing the first compound phase, the second semiconductor layer being adapted to react with the metal silicide layer; and
forming a metal silicide layer showing a second compound phase by causing the second semiconductor layer and the metal silicide layer showing the first compound phase to selectively react with each other.
Preferably, the step of forming a metal silicide layer showing the second compound phase is conducted under a condition where the reaction of the second semiconductor and the metal silicide showing the first compound phase has preference to the reaction of the first semiconductor and the metal silicide showing the first compound phase.
Preferably, the metal silicide is cobalt silicide and the metal silicide showing the first compound phase is CoSi, while the metal silicide showing the second compound phase is CoSi2.
Preferably, the first semiconductor layer is a single crystal silicon layer and the second semiconductor layer is an amorphous silicon layer.
Preferably, the step of forming a metal silicide layer showing the second compound phase is a heat treatment step conducted at temperature between 550xc2x0 C. and 650xc2x0 C.
In another aspect of the invention, there is provided a semiconductor device comprising:
source and drain regions formed in a single crystal silicon layer and separated from each other;
a gate insulating film formed between the source region and the drain region on the single crystal silicon layer;
a gate electrode formed on the gate insulating film; and
a metal silicide layer formed on the source region and the drain region;
the concentration of metal atoms in the source region and the drain region being not higher than 1xc3x971019 cmxe2x88x923;
the depth of the pn junction formed by the drain region and the single crystal silicon layer being not greater than 100 nm.
Preferably, the metal silicide is cobalt silicide and the metal atoms are cobalt atoms, not less than 17/35 of the film thickness of the metal silicide layer protruding over the single crystal silicon layer.
Preferably, the semiconductor device further comprises a silicon layer arranged on the metal silicide layer and electrically connected to the source region and the drain region.
This invention is based on the finding of the inventors of the present invention as described below.
For LSI manufacturing, compound formation between Si and Co (silicidation reaction) is commonly performed by applying a Co layer on a silicon substrate and then subjecting them to a heat treatment. At low temperature, CoSi phase is formed first. An annealing at a higher temperature promotes phase transition from CoSi to CoSi2. The CoSi2 phase shows a lower electric resistivity than that of CoSi and thus is used as a final form of the silicide layer for the LSI application.
As described in FIG. 6, it is an inherent nature of CoSi2 formation that Co atoms outburst into the silicon substrate during the silicidation reaction and then generate the leakage current. The inventors of the present invention further tried to identify the exact moment of the Co outburst during the silicidation reaction. FIG. 1 shows depth profiles of Co atom in the silicon substrate after the formation of the CoSi phase and after the transition to the CoSi2 phase measured by SIMS from the backside of the substrate (i.e., the profiles are free from knock-on effects). Evidently, Co outbursts at the time of the phase transition into CoSi2. And, notably, formation of CoSi phase alone does not induce sizable Co migration into the silicon substrate.
Moreover, the inventors of the present invention found that the temperature of the phase transition from CoSi to CoSi2 strongly depends on the physical state of silicon substrate. FIG. 2 plots sheet resistance of silicide layers as a function of temperature of a rapid thermal annealing (RTA) applied after CoSi formation on A: a single crystal silicon and B: an amorphous silicon layer produced by As implantation of 1xc3x971015 cmxe2x88x922 dosage. The RTA was performed with a ramping rate of 100xc2x0 C./sec in a nitrogen atmosphere. Obviously, a sharp drop of the resistance signals a phase transition from a high-resistivity CoSi phase to a low-resistivity CoSi2 phase. Regarding the silicidation on the single crystal silicon, the phase transition occurs in a temperature range between 650xc2x0 C. and 700xc2x0 C. On the other hand, on the amorphous silicon, the phase transitional ready progresses at around 550xc2x0 C.
On the basis of the above observations, the inventors of the present invention came to find a method of manufacturing a semiconductor device, which will be described below.
Firstly, as shown in FIG. 3A, a single crystal silicon substrate 1 operating as first semiconductor layer and having source and drain regions 2, 3 formed therein and separated from each other, a gate insulating film 4 formed between the source region 2 and the drain region 3 on the single crystal silicon layer 1 and a gate electrode 5 formed on the gate insulating film is prepared. In FIG. 3A, reference numeral 6 denotes an extended source region and reference numeral 7 denotes an extended drain region, whereas reference numeral 8 denotes a device isolating insulating layer and reference numeral 10 denotes the sidewalls of the gate electrode. Then, a metal silicide (CoSi) layer (not shown) showing a first compound phase is formed on the source region 2, the drain region 3 and the gate electrode 5. More specifically, a Co layer (not shown) is formed on the source region 2, the drain region 3 and the gate electrode 4 and subjected to a first heat treatment process to produce layers 501, 502 and 503 showing a CoSi phase. The first heat treatment condition for producing the CoSi phase is that of suitably conducting a rapid thermal annealing process in a temperature range between 450xc2x0 C. and 500xc2x0 C. Any possible production of a CoSi2 phase should be effectively suppressed under this condition. It is possible to form CoSi layers 501, 502, 503 respectively on the regions 2, 5, 3 in a self aligning manner by wet etching the remaining Co that is left unreacted. Thereafter, an amorphous silicon layer 600 is formed as second semiconductor layer on the metal silicide layers showing the first compound phase. The amorphous silicon layer 600 is adapted to react with the metal silicide layer.
Subsequently, as shown in FIG. 3B, the semiconductor layer 600 and the metal silicide layer showing the first compound phase are made to selectively react with each other to form metal silicide layers 511, 512, 513 showing a second compound phase respectively on the source region 2, the gate electrode 5 and the drain region 3. When a second heat treatment is conducted after depositing the amorphous silicon layer 600, theoretically, a reaction of phase transition to CoSi2 could take place at the interface between the amorphous silicon layer 600 and the CoSi layers 501, 502, 503, as well as at the interface between CoSi layers 501, 502, 503 and the crystal silicon substrate below. However, if the second heat treatment is conducted at temperature between 550xc2x0 C. and 650xc2x0 C., as shown in the FIG. 2, it is possible to make the reaction of phase transition selectively progress between the amorphous silicon layer and upper zones of the CoSi layers 501, 502, 503, while phase transition to CoSi2 phase does not progress between the single crystal silicon and lower zones of the CoSi layers 501, 502, 503. During this heat treatment, Co atoms migrate from the CoSi layers 501, 502, 503 only into the amorphous layer above and react with the silicon atoms to form CoSi2 layers. If the second heat treatment is conducted in this way, the reaction of phase transition does not proceed between CoSi layers 501, 502, 503 and the crystal silicon substrate below.
Thus, as shown in the FIG. 1, no metal atoms get to the source/drain junction interface formed in the substrate, hence generating no leakage.
Moreover, because no reaction proceeds between CoSi layers and the crystal silicon substrate below, no silicon is consumed during the heat treatment and CoSi2 layers grow one-sidedly into the upper zone of the amorphous silicon layer. Therefore, the CoSi2 layers come to be raised partly over the original surface (the channel forming surface) of the silicon substrate, providing an effect similar to the one obtained with an elevated source/drain structure. Since CoSi2 layers can be formed with a uniform film thickness and raised over the original surface of the silicon substrate, the distance from the bottom of the CoSi2 layers to the source/drain junctions increases. The increased distance strongly suppresses possible junction leakage even further together with the above-explained restrained diffusion of Co atoms.
Additionally, by forming CoSi layers in a self-aligning manner, depositing an amorphous silicon layer thereon and conducting the second heat treatment in this way, the CoSi2 layers can be obtained also in a self-aligning manner over the source region 2, the drain region 3 and the gate electrode 5.
Consequently, by removing the remaining amorphous silicon layer, it is now possible to obtain a SALICIDE type MOSFET having an elevated source/drain structure, where diffusion of Co atoms into the substrate is suppressed in a self-aligning manner.
Otherwise, by keeping the remaining amorphous layer in a way that it maintains an electrical contact with extended source/drain region, a channel current can be made to flow from/into the silicide layer through both of the upper and lower interfaces. Then, the contact resistance between the CoSi2 layers and the source/drain regions can be reduced to about a half.
Furthermore, with a manufacturing method according to the invention, the depth of the extended source/drain regions can be determined freely without concerns over the leakage current that may otherwise occur due to the silicidation. It provides an extra latitude in the device designing to prevent the short channel effect and enhance the controllability of the threshold voltage.
Besides, the length of the gate sidewalls (and hence the length of the extended source/drain regions) can be held to 100 nm or less so as to improve the device drivability because the leakage-free nature of the present manufacturing method removes a requirement for thick sidewalls to prevent the leakage induced by the silicidation.
In terms of the gate electrode, since metal atoms are prevented from diffusing into the polycrystalline silicon of the gate electrode, they no longer reach and degrade the gate insulator below. Therefore, the height of the gate electrode can be minimized to a great advantage to the subsequent lithography and planarization steps
Adding to the above benefits, since the CoSi2 layers grow freely into the upper amorphous silicon layer, any volumetric change induced by the silicidation and consequent generation of mechanical stress can be effectively avoided to eliminate any additional cause of producing leakage from the junction.
It should be noted here, with a manufacturing method according to the invention, the concentration of metal atoms in the source region and the drain region is held to 1xc3x9710xe2x88x9219 cmxe2x88x923 or less and the depth of pn junction formed by the source region or the drain region and the single crystal silicon layer can be made to be not more than 100 nm. Thus, the short channel effect is prevented and the controllability of the threshold voltage is enhanced.
In terms of the intrinsic properties of the silicidation, if 10 nm-thick Co is deposited on the silicon substrate in the first heat treatment step of the manufacturing method according to the invention, 20 nm-thick CoSi is formed, of which about 18 nm of the CoSi layer is embedded into the silicon substrate and about 2 nm protrudes over the surface of the silicon substrate. If an amorphous silicon layer is additionally deposited thereon and subjected to the second heat treatment step, the CoSi layer consumes the silicon atoms above and transforms into CoSi2. As a result, CoSi2 encroaches on the upper amorphous silicon layer and about 17 nm grows above the original silicon substrate. On the other hand, an about 18 nm-thick CoSi2 is remains as before below the original silicon substrate. Thus, of the resulting 35 nm-thick CoSi2 layer formed by the manufacturing method according to the present invention, 17 nm or more is elevated over the surface of the original silicon substrate. In other words, the metal silicide formed on the silicon substrate is raised by 17/35 or more of the entire thickness. Its exact value is determined by the physical properties of silicon.